Finite state machine is a tough nut to crack

Day 47

     Professor Porter goes into great detail about how the finite state machine works and it's theory of operation. However he does not show a full blown schematic, but there is a layout in the various downloaded image files, for this vital portion of the computer. He somewhat seems to leave much of this area up to you to figure out. However, this is the some of the truly uncharted territory for me I understand the abstract of this system but cannot quite wrap my brain around the full function of this. I understand that it is essentially breaking out the clock pulses so that each individual pulse can control the specific portion of the computer it has to but the underlying control structure it orchestrates is eluding me for the moment. This lack of understanding is somewhat exacerbated by professor Porter's desire that those control systems be figured out by the student as well. This is an area I need to study more and shows that perhaps I should go back and try to better understand how all of these functions are executed. This is the plan starting with today's post.

     So instead of killing myself by jumping around in the paper any further I am just going to mosey on from where I left off with the adder. This brings us to the zero detect circuit it's function is very simple it's use, however is not immediately apparent to my eye unless it can be used to call a halt or perhaps if factoring a number but I am not sure beyond those 2 cases hopefully it's need will be demonstrated in the future. The sign bit is discussed next and it is simply represented by the most significant bit on the bus this means that instead of a full 8 bit word we a technically only working with 7 bits for numbers and 1 bit for sign. This is actually somewhat confusing as you look through the paperwork as in some diagrams professor Porter has the sign bit broken out from the ALU output but in many of the block diagrams but in the reference materials and schematics it is nowhere to be seen so this is how I ended up drawing this conclusion. For the ALU functions this makes sense as any function performed on this bit to compare it to the sign bit on the other register will result the mathematically proper answer. the only issue with it I have is if a number carry's over to the 8th bit it will give an incorrect answer, but these kind of non error errors can be seen in many older systems and in the design history of several programming languages. It is simply misleading in various diagrams and the like.

     The 3 to 8 decoder shown in professor Porter's design has been replaced in mine by the 4 to 16 design which is a simple extension of his principals. This is done to accommodate the added functions I would like to include in my build. So far we have added a right shift but I am considering adding a subtract function if it is plausible. Other considerations so far are a constant (not necessarily as part of the decoders function), A NOT function for the "C" register, a NAND function, and finally a potential multiplication function.  As these ideas represent only 4 or 5 additions to the decoder they would be no problem for that end, the limiting factor will be my desire to expand the ALU and by extension the part count. This does leave me open to adding other functions that may use unused portions of the existing system or combining some functions like in the logic block. For instance the NOT "C" function or the NAND function could be incorporated into the existing logic block and as such would add very little overhead but almost all of the other functions will add to the parts count by at least 10 relays. If I attempt this less expensive single or double pole relays may find their way into the project. Many portions of this are still up in the air. Another modification I will be making to the decoder is the change of the "000" input going from ADD to "Not Used" this is a clearly stated flaw in professor Porter's design and 1 that I will build out of my design. the simple truth to this is that it takes no effort to send that "000" down the line which means that any time the system does not need the ALU to output then it needs only cut power from the decoder. The original design used "111" as the "Not Used" which meant that power to the decoder could not be cut unless you wanted to ADD.


      Wednesday we will be talking about the overall system architecture as a warm up for breaking down those control systems and what they entail. I will be focusing on the various registers and what their functions are in the operation of the computer.