Day 43
The adder is discussed in some detail in a few places but it's design is identical to that of Konrad Zuse from the 1941 relay computer he built. I have included a Fritzing diagram of the single bit and the full 8 bit chain in the Google Drive folder I have only done a screencap of the single bit as to zoom out enough to see the full chain of adders makes it virtually useless as an aid.
On top of the discussion in Harry's paper on the he also points us to a Java applet demonstrating the adders function. I have not jumped through the hoops necessary to get this to work on my computer as I keep Java on a very tight leash for security's sake, but it looks fascinating. Both give a decent rundown of the history of the adder though the Java page gives a bit more detail I will not attempt to mess with what seems to me so succinct and as such will be following Harry's lead and simply copying this full adder over to my design, which is even used in the RC2 design unaltered. The other function of this circuit is incrementing this function will take Bin and output a +1 to it instead of adding it to Cin this is accomplished by inputting a 1 to the Carry in on the 0 bit a a simple control circuit for these functions is shown in the RC2 plans and I will likely be basing my design on it.
This is the last of the functional portion of our design from here we get into the program counter and the memory and the various control circuits and putting all of these circuits together with those controls shows the 1 major flaw in this design besides speed. That is inefficiency the adder all of the logic functions and the shift operations all happen regardless of weather or not they are needed we simply select the 1 we want to go out onto the bus this design while simple is very inefficient in power consumption and in the lack of ability to multitask. In modern computers these functions can all be happening to different sets of numbers simultaneously or nearly as such. this is called multi-threading and it drastically helps to increase speed of computing as it means 2 or more calculations are happening at 1 time, which effectively doubles, triples, or quadruples output speeds. This effect could be performed in our design but it would come at the cost of greatly increased complexity and cost several new registers would need to be added to the design to store the numbers as well as a drastic overhaul of the control and mode selection system and the addition of at least 1 more bus or a widening of the existing bus. While these changes would be fun to make and I am not throwing them aside for a long term project the lack of real world use cases for this device limit even my desire to chase that rabbit. For now I think this system will suffice for my purposes.
Next I do believe some design and discussion on the finite state machine will be in order. This will start giving structure to the underlying control systems we will be building in later. Then after or during that we will start our mock ups of the various portions of the system we have already discussed. I am working on a build up board design to make the build ups go more smoothly and allow us to see each circuit in detail.
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