Register Storage

Day 13

     I am having a lot of fun getting lost in the minutia of this build and there are a lot of little nuances to it to get lost in but the real story is how all of this relates to the architecture of modern computing. While the components have changed, shrunk, and sped up significantly the basic functions of those components has not changed. The transistors on a modern CPU act in the same way as these relays except they switch much faster and with much lower voltage and current. These similarities get to the heart of why I'm undertaking this little adventure, I have long been a lover and user of computers and electronics now it is time to fully understand what is going on with them. The hope is to become not just another brick in the consumer wall but to be an active participant of the culture I have loved for decades.

     We've already looked at the shift register now let's look at the storage register the basics of it is a simple latch circuit where only 1 switch of the relay is used and the common of that switch and 1 side of the coil are connected the N/O contact is connected to a "Hold Line" that allows bits loaded to be stored as long as the hold line is powered. this memory buffer is easily cleared by just dropping power to the hold line. At that point the only relays that will stay active are the high bits on the bus but if the bus should change it's value then so will the high bits in the register until the hold line is activated again then any high bits will remain high even if the bus changes state.  The problem comes in when the bus changes high bits will stay high but low bits that go high will then latch high as well to prevent this we use the same type of enable circuit from the ALU to either allow or disallow the bus contents to be loaded onto the register. 

     To allow the register to be loaded from the bus or to load onto the bus we will use 2 control lines and 2 NOT gates the control lines are LOAD and SELECT and they are connected together by the 2 NOT gates as well as the register the select line is connected to the enable circuit's control line and to 1 NOT gate the other side of the NOT is connected to the other NOT and the HOLD line of the register itself the other side of the second NOT is connected to the LOAD line. This simple setup gives us the clear function before any loading of the register from the bus and allow us to write to the bus as well. As listed this circuit will create a feedback loop in the Hold line which would destroy our data so instead of using a single NOT on the LOAD line we use a split NOT separating out the NOT function to 1 switch and the Hold line to another both powered by the same common this prevents the feedback of any high bits from causing oscillations in the Hold line control.

     Next I believe we are going to skip to the clock circuit to get an in depth look at it's function and what impact it has on all of the things we've done so far. At the end of the day the clock is important as without it we would be hand advancing this computer and that would reduce the automation effect of it. not to mention all the tedium it would entail.